In various memories, data may be read from memory cells in respective memory sections and provided to external devices via lines, such as global data lines. Sense amplifiers are typically located at an end of these lines and are configured to sense data on the lines in response to one or more control signals and amplify the data. Typically, sense amplifiers are shared between multiple sets of lines and are selectively coupled to individual sets during memory operations, allowing the sense amplifiers to sense data on one set of lines at a time. For example, sense amplifiers may be selectively coupled to the sets of lines of two different sections of memory with which the sense amplifiers are shared.
As memory density and complexity has increased over time, the data lines extending through memories have increased in both length and number. Line length in particular has been a design constraint. For example, the greater the line length the greater the amount of time required to pre-charge the line and the further a line extends from a sense amplifier the greater the amount of time required to drive the line to a condition that may be accurately sensed by the sense amplifier.
In the past, one approach to solve this issue has been to shorten the length of lines extending through memory sections. Although this may reduce the time needed to change the signal states on lines, this approach is not always a feasible solution to achieve necessary reduction in memory timings. For example, having shorter lines may require more sets of sense amplifiers to provide a memory density comparable to memories having fewer sets of sense amplifiers and longer lines. Moreover, additional design constraints have arisen from increased complexity in memories, for example, control logic used to couple and decouple sense amplifiers from lines. In accounting for this additional complexity, memory timings must be relaxed, and achieving desired memory performance is more difficult.